• Project Assistant, MTech
• Algorithms and Complexity Group
• TU Wien
• Favoritenstraße 9–11
• 1040 Wien, Austria

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• Room: HA 04 06
• Email: vaidyanathan [at] ac [dot] tuwien.ac.at
• Web: aditya95sriram.github.io | ac.tuwien.ac.at/vaidyanathan

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Research Interests

• Parameterized Complexity
• SAT Encodings
• Graph Width Parameters

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Current Position

• I am a PhD student in the Doctoral College Logical Methods in Computer Science
• Under the supervision of Stefan Szeider
• Supported by FWF (projects P32441 and W1255) and by the WWTF (project ICT19-065)
• Part of the Algorithms and Complexity Group

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Education

• MTech in Computer Science from Indian Institute of Technology Gandhinagar
• BTech in Electrical Engineering from Indian Institute of Technology Gandhinagar

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Publications

1. Vaidyanathan Peruvemba Ramaswamy, Stefan Szeider - Turbocharging Treewidth-Bounded Bayesian Network Structure Learning. To appear in: Proceeding of AAAI-21, the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021. [arxiv]
2. Vaidyanathan Peruvemba Ramaswamy, Stefan Szeider - MaxSAT-Based Postprocessing for Treedepth In: Proceedings of CP 2020, the 26th International Conference on Principles and Practice of Constraint Programming (Helmut Simonis, ed.), volume 12333 of Lecture Notes in Computer Science, pages 478–495, 2020, Springer Verlag. [tech-report]

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Outside research

I am also interested in twisty puzzles, table tennis/ping-pong and co-op video games.