- Head of the FORSYTE Group.
- Coordinator of Research Focus “Computational Intelligence” at TU Wien.
- Speaker of Doctoral College “Logical Methods in Computer Science”.
- Member of the Academic Senate of TU Wien.
theory and practice of model checking, abstraction, program verification, program synthesis, testing, formal methods in software engineering, embedded systems, and computer security
Helmut Veith is a professor of Computer Science at Vienna University of Technology, Austria, and an Adjunct Professor at Carnegie Mellon University, Pittsburgh. Prior to his appointment in Vienna, he had professor positions at TU Darmstadt (2008-2009) and TU Munich (2003-2008). He is the speaker of the Doctoral College "Logical Methods in Computer Science", and vice-speaker of the Austrian research network "Rigorous Systems Engineering". Veith is a coeditor of the forthcoming Handbook of Model Checking, PC co-chair of LPAR 2008, CSL 2010, CAV 2013, and FMCAD 2015, and co-chair of the Vienna Summer of Logic 2014, the largest conference in the history of logic. He has published more than 100 papers in computer-aided verification, software engineering, computer security, and logic in computer science. He is best known for his role in the development of Counterexample-guided Abstraction Refinement (CEGAR) which is a key ingredient in modern model checkers for software and hardware. His awards include a PhD award sub auspiciis praesidentis by the Austrian president, and an ACM Distinguished Paper Award for work on the software model checker MAGIC.